Integrated Circuit Design Verification Engineer

About the role

Join a multidisciplinary group creating display chips for augmented reality glasses. The role focuses on verifying those integrated circuits from planning through sign-off.

What you will do

• Build and maintain testbenches using UVM and assertion methods
• Write and carry out verification plans covering functional and code coverage
• Use Siemens Questa for simulation and debugging
• Define and set up tooling, then automate the flow
• Coordinate with digital, analog, software and verification colleagues

What they look for

• Solid grasp of UVM and SystemVerilog verification methods
• Hands-on knowledge of digital functional simulation with tools like Siemens Questa
• Good practice writing Verilog RTL
• Scripting skills with TCL, Make, Perl, Python or shell in Linux
• At least ten years of ASIC design verification experience
• Bachelor's or master's degree in electrical engineering, or comparable experience

Nice to have

• Experience owning the full verification process from planning to sign-off
• Familiarity with the Siemens UVM Framework
• Background in emulation or RTL design
• Knowledge of video and display systems, MIPI, AMBA, I2C, SPI and embedded microcontrollers